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    Memory controller, memory buffer chip and memory system
    1.
    发明授权
    Memory controller, memory buffer chip and memory system 有权

    公开(公告)号：US10346090B2

    公开(公告)日：2019-07-09

    申请号：US15287917

    申请日：2016-10-07

    Applicant: SK hynix Inc.

    Inventor： Young-Suk Moon ,  Hong-Sik Kim

    IPC: G06F3/06 ,  G06F13/16

    Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.

    Semiconductor device configured to control a wear leveling operation and operating method thereof
    2.
    发明授权
    Semiconductor device configured to control a wear leveling operation and operating method thereof 有权

    公开(公告)号：US10157148B2

    公开(公告)日：2018-12-18

    申请号：US14512885

    申请日：2014-10-13

    Applicant: SK hynix Inc.

    Inventor： Young-Suk Moon ,  Hong-Sik Kim

    IPC: G06F12/123 ,  G06F12/0868

    Abstract: A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.

    Integrated circuit system
    3.
    发明授权
    Integrated circuit system 有权

    公开(公告)号：US10275385B2

    公开(公告)日：2019-04-30

    申请号：US15441925

    申请日：2017-02-24

    Applicant: SK hynix Inc.

    Inventor： Hong-Sik Kim ,  Young-Suk Moon

    IPC: G06F13/42 ,  G06F11/07 ,  G06F13/16

    Abstract: An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.

    Memory controller and request scheduling method using request queues and first and second tokens
    4.
    发明授权
    Memory controller and request scheduling method using request queues and first and second tokens 有权

    公开(公告)号：US10157023B2

    公开(公告)日：2018-12-18

    申请号：US15441818

    申请日：2017-02-24

    Applicant: SK hynix Inc.

    Inventor： Young-Suk Moon ,  Hong-Sik Kim

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/37

    Abstract: A memory controller includes a plurality of request queues for storing requests transmitted from corresponding host devices among a plurality of host devices, and a token information generation unit for generating information related to the numbers of first and second tokens corresponding to the plurality of respective host devices. The memory controller also includes a request scheduler for selecting repeatedly and sequentially the plurality of request queues, and outputting requests stored in a selected request queue, by using the first and second tokens, wherein the request scheduler outputs one request per one first token and, when first tokens are all consumed, outputs one request per one second token. The scheduler may output requests according to a first-ready first-come first-served (FR-FCFS) rule when using a first token, and output requests according to a first-ready (FR) rule when using a second token. The number of first tokens and second tokens may depend on characteristics of the host devices. A bandwidth control unit may control the number of first and second tokens based on bandwidth. The scheduler may stop outputting requests of a currently selected request queue, and output requests of a request queue corresponding to a top-priority host device.

    Semiconductor device and operating method thereof
    5.
    发明授权
    Semiconductor device and operating method thereof 有权
    半导体器件及其操作方法

    公开(公告)号：US09129672B2

    公开(公告)日：2015-09-08

    申请号：US13964489

    申请日：2013-08-12

    Applicant: SK hynix Inc.

    Inventor： Young-Suk Moon ,  Yong-Kee Kwon ,  Hong-Sik Kim

    IPC: G06F12/00 ,  G11C19/00 ,  G06F3/06 ,  G11C11/4078 ,  G11C11/408 ,  G11C8/08

    CPC classification number: G11C19/00 ,  G06F3/0614 ,  G06F3/0619 ,  G11C8/08 ,  G11C11/4078 ,  G11C11/408

    Abstract: A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register.

    Abstract translation: 半导体器件包括：第一级寄存器，用于存储发生在第一周期的事件;第二级寄存器，用于存储在比第一周期短的第二周期内发生的事件;以及控制器，用于控制第二级寄存器以从第二级选择事件 将具有大于第二阈值的参考值的每个寄存器寄存到第一级寄存器，并且用于控制第一级寄存器以存储从第二级寄存器中选择的事件。

    Memory buffer chip, memory system and method of controlling the memory buffer chip
    7.
    发明授权
    Memory buffer chip, memory system and method of controlling the memory buffer chip 有权

    公开(公告)号：US10990322B2

    公开(公告)日：2021-04-27

    申请号：US16422858

    申请日：2019-05-24

    Applicant: SK hynix Inc.

    Inventor： Young-Suk Moon ,  Hong-Sik Kim

    IPC: G06F3/06 ,  G06F13/16

    Abstract: A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.

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