公开(公告)号：US09160324B2

公开(公告)日：2015-10-13

申请号：US14082850

申请日：2013-11-18

Applicant: SK hynix Inc.

Inventor： Tae-Jin Hwang

IPC: H03L5/00 ,  H03K6/04 ,  H03K6/02

CPC classification number: H03K6/04 ,  H03K6/02

Abstract: A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.

Abstract translation: 缓冲电路包括适于缓冲输入信号并输出​​输出信号的缓冲单元和适于根据输出信号调整输入信号的转换速率的反馈控制单元。

公开(公告)号：US09094244B2

公开(公告)日：2015-07-28

申请号：US13841941

申请日：2013-03-15

Applicant: SK hynix Inc.

Inventor： Tae-Jin Hwang

IPC: H04B3/04 ,  H04L25/02

CPC classification number: H04L25/0272

Abstract: A receiver circuit includes a first differential amplification unit including a variable load section, and configured to receive first and second input signals, and to generate first and second output signals, which are amplified based on an impedance value of the variable load section and a voltage difference between the first and second input signals, a second differential amplification unit configured to receive the first and second output signals and to generate a third output signal based on a voltage difference between the first and second output signals, and a signal generating unit configured to generate an equalization signal for controlling the variable load section based on the third output signal.

Abstract translation: 接收器电路包括：第一差分放大单元，包括可变负载部分，并且被配置为接收第一和第二输入信号，并且生成第一和第二输出信号，其基于可变负载部分的阻抗值和电压 所述第一和第二输入信号之间的差异;第二差分放大单元，被配置为接收第一和第二输出信号，并且基于第一和第二输出信号之间的电压差产生第三输出信号;以及信号生成单元， 基于第三输出信号产生用于控制可变负载部分的均衡信号。

公开(公告)号：US20130076401A1

公开(公告)日：2013-03-28

申请号：US13680239

申请日：2012-11-19

Applicant: SK HYNIX INC.

Inventor： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

IPC: H03K5/153

CPC classification number: H03K5/153

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

公开(公告)号：US08890613B2

公开(公告)日：2014-11-18

申请号：US13718421

申请日：2012-12-18

Applicant: SK Hynix Inc.

Inventor： Tae-Jin Hwang

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45248 ,  H03F2203/45466 ,  H03F2203/45641 ,  H03F2203/45674

Abstract: A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal.

Abstract translation: 信号放大电路包括：差分放大器，被配置为接收第一信号和第二信号并产生输出信号;差分放大器，被配置为接收第一和第二信号并产生输出信号; 以及控制器，被配置为使用所述输出信号来控制在所述差分放大器中流动的电流量。

公开(公告)号：US08461878B2

公开(公告)日：2013-06-11

申请号：US13680239

申请日：2012-11-19

Applicant: SK Hynix Inc.

Inventor： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

IPC: H03K5/153

CPC classification number: H03K5/153

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。