公开(公告)号：US12087677B2

公开(公告)日：2024-09-10

申请号：US17248382

申请日：2021-01-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Clemens Ypil Quinones ,  Bigildis Dosdos ,  Jerome Teysseyre ,  Erwin Ian Vamenta Almagro ,  Romel N Manatad

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/482 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3142 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49568 ,  H01L23/544 ,  H01L23/562 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32258

Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.

公开(公告)号：US11791247B2

公开(公告)日：2023-10-17

申请号：US17305396

申请日：2021-07-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erwin Ian Vamenta Almagro ,  Maria Clemens Ypil Quinones ,  Romel N. Manatad ,  Maria Cristina Estacio ,  Elsie Agdon Cabahug

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/49541 ,  H01L23/31 ,  H01L23/5226

Abstract: Semiconductor packages may include a lead frame, one or more semiconductor die coupled with the lead frame, and an interposer coupled with the lead frame and with at least one of the one or more semiconductor die. The interposer in implementations includes an electrically conductive material coupled with an electrically insulative material. The interposer may be coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame. The interposer may facilitate a gate node of the package being fully encapsulated within the package without being exposed through an encapsulant of the package. Fully encapsulating the gate node within the package may allow a contact pad of another node to have a larger area exposed through the encapsulant to provide greater heat transfer to a printed circuit board (PCB).