公开(公告)号：US20170201213A1

公开(公告)日：2017-07-13

申请号：US15399059

申请日：2017-01-05

申请人： SDRF EURL

发明人： BIAGIO BISANTI ,  ERIC DUVIVIER ,  LORENZO CARPINETO ,  STEFANO CIPRIANI ,  FRANCESCO COPPOLA ,  GIANNI PUCCIO ,  RÉMI ARTINIAN ,  FRANCOIS MAROT ,  VANESSA BEDERO ,  LYSIANE KOECHLIN

IPC分类号： H03B5/04 ,  H03B5/12

CPC分类号： H03B5/04 ,  H03B5/1218 ,  H03B5/1231 ,  H03B5/124 ,  H03B5/1243 ,  H03B2200/0006 ,  H03B2200/0008 ,  H03B2200/004 ,  H03B2201/0208 ,  H03L7/099

摘要： A variable frequency oscillator comprising a first transistor (10) and a second transistor (20); wherein the first transistor (10) has a first terminal—collector—which is connected to a reference voltage, and a second terminal—emitter—which is connected to a first terminal of a first current source (13), which second terminal is connected to ground, and a third terminal—base—connected to a first terminal of a first inductor (14) and to a top terminal of a first capacitor (11), wherein the first capacitor (11) has a bottom terminal which is connected to the second terminal—emitter—of the first transistor (10) but also to a top terminal of a second capacitor (12) having a bottom terminal being connected to ground; wherein the second transistor (20) has a first terminal—collector—which is connected to a reference voltage, and a second terminal—emitter—which is connected to a first terminal of a second current source (23), which second terminal is connected to ground, and a third terminal—base—connected to a first terminal of a second inductor (14) and to a top terminal of a third capacitor (21), wherein the third capacitor (21) has a bottom terminal which is connected to the second terminal—emitter—of the second transistor (20) and also to a top terminal of a fourth capacitor (22) having a bottom terminal connected to ground; wherein the first and second inductors (14, 24) have a second terminal which are connected via a circuit (100) achieving variable capacitance, so as to form a circuit connecting in series all passive components composing the LC tank, so as to achieve a variable capacitance which can be used for performing a tuning of the oscillator, and wherein the second capacitor (12) and the fourth capacitor (22) are both connected to the physical ground thereby avoiding a 2nd harmonic common mode oscillation that might dominate over the differential fundamental one and might destroy the first and the second transistors (10, 20).

公开(公告)号：US20170201262A1

公开(公告)日：2017-07-13

申请号：US15399040

申请日：2017-01-05

申请人： SDRF EURL

发明人： BIAGIO BISANTI ,  ERIC DUVIVIER ,  LORENZO CARPINETO ,  STEFANO CIPRIANI ,  FRANCESCO COPPOLA ,  GIANNI PUCCIO ,  REMI ARTINIAN ,  FRANCOIS MAROT ,  VANESSA BEDERO ,  LYSIANE KOECHLIN

IPC分类号： H03L7/23 ,  H03L7/099 ,  H03L7/093

CPC分类号： H03L7/23 ,  H03L7/093 ,  H03L7/099 ,  H03L7/185

摘要： A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: Fout=(N1/R1+ . . . +Nn/Rn)*Fcro where N1 and R1 are the dividing values of the first auxiliary loop and Ni and Ri with i=2 . . . n−1 being the dividing ratios of any possible further auxiliary loop; and Fcro is the frequency generated by VCO, whereby the multiloop circuit is configured with dividing values which optimizes a cost function F.