公开(公告)号：US10103133B2

公开(公告)日：2018-10-16

申请号：US15659065

申请日：2017-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eugene Jinglun Tam

IPC: G11C5/06 ,  H01L25/18

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.

公开(公告)号：US09728526B2

公开(公告)日：2017-08-08

申请号：US13904770

申请日：2013-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eugene Jinglun Tam

IPC: H01L25/18 ,  G11C5/06

CPC classification number: H01L25/18 ,  G11C5/06 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.

公开(公告)号：US09703702B2

公开(公告)日：2017-07-11

申请号：US14139164

申请日：2013-12-23

Applicant: SanDisk Technologies LLC

Inventor： Eugene Jinglun Tam

IPC: G06F12/08 ,  G11C5/00 ,  G11C29/00 ,  G11C8/12

CPC classification number: G06F12/08 ,  G06F2212/1016 ,  G06F2212/2022 ,  G11C5/00 ,  G11C8/12 ,  G11C29/83 ,  G11C29/88

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.