公开(公告)号：US20160240252A1

公开(公告)日：2016-08-18

申请号：US15042516

申请日：2016-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUN CHU OH ,  JUN JIN KONG ,  YOUNG BAE KIM ,  HONG RAK SON ,  PIL SANG YOON ,  HAN SHIN SHIN

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/1006 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0076

Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

Abstract translation: 具有多个存储单元的电阻式存储器系统包括具有电阻性存储单元阵列和控制器的存储器件。 控制器通过对输入数据进行编码来产生要写入存储单元阵列的写入数据，使得输入数据对应于存储单元可能具有的擦除状态和多个编程状态。 编码输入数据使得分配了第一编程状态的存储器单元的数量和分配有第二编程状态的存储单元的数量中的至少一个小于擦除状态下的至少一个存储单元，并且 其他编程状态。 第一编程状态在多个编程状态中具有最高的电阻电平，并且第二编程状态在多个编程状态中具有第二高的电阻电平。

公开(公告)号：US20200020613A1

公开(公告)日：2020-01-16

申请号：US16256895

申请日：2019-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG BAE KIM

IPC: H01L23/49 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a flip chip coupled to the package substrate, an interposer stacked on the flip chip and including a first terminal and a second terminal at an upper surface thereof, a bonding wire which connects the first terminal and the package substrate and a mold layer which covers the interposer, the flip chip and the bonding wire. The mold layer has a signal hole which exposes the second terminal, and at least one dummy hole spaced apart from the signal hole on an upper surface of the interposer.