公开(公告)号：US20180108633A1

公开(公告)日：2018-04-19

申请号：US15499272

申请日：2017-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOOJEOUNG PARK ,  BONA BAEK ,  YONGHO KIM

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/0612 ,  H01L2224/13012 ,  H01L2224/14104 ,  H01L2224/1412

Abstract: A semiconductor device includes a semiconductor chip, pads provided on the semiconductor chip, and insulating patterns provided on the semiconductor chip. The insulating patterns having openings exposing the pads, and conductive patterns are provided in the openings and coupled to the pads. When viewed in a plan view, two opposite ends of the pads are spaced apart from the conductive patterns and two opposite ends of the conductive patterns are spaced apart from the pads. Additionally, when viewed in a plan view, the conductive patterns include a first conductive pattern whose length is parallel to a first direction and a second conductive pattern whose length is parallel to a second direction. The first and second directions are oblique to each other.

公开(公告)号：US20180068715A1

公开(公告)日：2018-03-08

申请号：US15611274

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HOONKI KIM ,  JONGHOON JUNG ,  YONGHO KIM

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.