公开(公告)号：US20140256101A1

公开(公告)日：2014-09-11

申请号：US14281482

申请日：2014-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Chang MOON ,  Sung-Min HWANG ,  Woonkyung LEE

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

Abstract: A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

Abstract translation: 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

公开(公告)号：US20130171809A1

公开(公告)日：2013-07-04

申请号：US13759584

申请日：2013-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun LEE ,  Woonkyung LEE

IPC: H01L21/36

CPC classification number: H01L21/36 ,  H01L21/02521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.

Abstract translation: 半导体器件具有包括单元阵列区域和围绕单元阵列区域的虚设图案区域的基板。 单元阵列区域包括具有从基板的单元阵列区域沿垂直方向延伸的多个单元有源柱的单元结构，并且包括交替层叠在基板上的单元栅极图案和单元栅极层间绝缘图案。 单元栅极图案和单元栅极层间绝缘图案具有面向单元活性柱的侧面。 虚设图案区域包括防潮结构。