公开(公告)号：US11468952B2

公开(公告)日：2022-10-11

申请号：US17191412

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Su Kim ,  Hyun Jin Choi ,  Alain Tran ,  Beom Kyu Shin ,  Woo Seong Cheong

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.