公开(公告)号：US20230019790A1

公开(公告)日：2023-01-19

申请号：US17742619

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsung KANG ,  Hyoungyol MUN ,  Sungdong CHO ,  Wonhee CHO

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

公开(公告)号：US20190155765A1

公开(公告)日：2019-05-23

申请号：US16034887

申请日：2018-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Woo LEE ,  Wonhee CHO

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02

Abstract: A method of operating a storage device controller which controls a storage device includes receiving a debugging data request command through a peripheral component interconnect express (PCIe) interface of the storage device controller from outside of the storage device controller, and storing debugging data in a register included in the PCIe interface.

公开(公告)号：US20230350578A1

公开(公告)日：2023-11-02

申请号：US18346627

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhee CHO ,  Dongeun SHIN

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/064 ,  G06F12/0246

Abstract: Each of a plurality of memory blocks of a nonvolatile memory device is divided into two or more wordline groups having different characteristics. A write command for at least two memory blocks among the plurality of memory blocks is received. During a first partial time interval included in an entire write time interval for two or more memory blocks, a data write operation is performed on a wordline group included in one memory block among the two or more memory blocks in response to a reception of an address for the one memory block. During a second other partial time interval included in the entire write time interval, a data write operation is performed on wordline groups included in the two or more memory blocks in response to a reception of an address for the two or more memory blocks.

公开(公告)号：US20210026553A1

公开(公告)日：2021-01-28

申请号：US16811682

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo KIM ,  Jaeyong JEONG ,  Myunghyun JO ,  Wonhee CHO

IPC: G06F3/06

Abstract: A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.