公开(公告)号：US20240220103A1

公开(公告)日：2024-07-04

申请号：US18231829

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyeon PARK ,  Dongeun SHIN ,  Jinhyuk LEE

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0688

Abstract: A method of operating a storage device including a plurality of nonvolatile memory devices and a storage controller, including: generating a parity chunk by performing a redundant array of independent disks (RAID) encoding on a plurality of data chunks; storing a data stripe including the plurality of data chunks and the parity chunk in a plurality of memory blocks included in the plurality of nonvolatile memory devices; and performing a direct read operation or an indirect read operation based on an operating state of the storage device such that in the direct read operation a target data chunk is directly read from the plurality of nonvolatile memory devices, and in the indirect read operation the target data chunk is generated by performing a RAID decoding.

公开(公告)号：US20230350578A1

公开(公告)日：2023-11-02

申请号：US18346627

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhee CHO ,  Dongeun SHIN

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/064 ,  G06F12/0246

Abstract: Each of a plurality of memory blocks of a nonvolatile memory device is divided into two or more wordline groups having different characteristics. A write command for at least two memory blocks among the plurality of memory blocks is received. During a first partial time interval included in an entire write time interval for two or more memory blocks, a data write operation is performed on a wordline group included in one memory block among the two or more memory blocks in response to a reception of an address for the one memory block. During a second other partial time interval included in the entire write time interval, a data write operation is performed on wordline groups included in the two or more memory blocks in response to a reception of an address for the two or more memory blocks.