公开(公告)号：US10930672B2

公开(公告)日：2021-02-23

申请号：US16524439

申请日：2019-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeon Cho ,  Hyeri Shin ,  Sung-Bok Lee ,  Yusik Choi ,  Sungyung Hwang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/24 ,  H01L27/22 ,  H01L23/535

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate including a cell array region, a connection region, and a block selection region between the cell array and connection regions, a stack structure including horizontal layers vertically stacked on the substrate, each of the horizontal layers including electrode portions extending in a first direction on the cell array and block selection regions and a connecting portion disposed on the connection region to connect the electrode portions in a second direction perpendicular to the first direction, and block selection gate electrodes intersecting sidewalls of the electrode portions of the horizontal layers on the block selection region. Each of the electrode portions includes a first semiconductor region having a first conductivity type on the cell array region and includes a channel dopant region having a second conductivity type different from the first conductivity type on the block selection region.