公开(公告)号：US20220102336A1

公开(公告)日：2022-03-31

申请号：US17246108

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwe CHO ,  Subin JIN

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G06F30/392

Abstract: An integrated circuit includes at least one decoupling cell, wherein the at least one decoupling cell includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and a number of the at least one P-type decoupling MOSFET is different from a number of the at least one N-type decoupling MOSFET.

公开(公告)号：US20240265184A1

公开(公告)日：2024-08-08

申请号：US18638199

申请日：2024-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwe CHO

IPC: G06F30/392 ,  G06F30/398 ,  G06F111/04 ,  H01L27/02

CPC classification number: G06F30/392 ,  G06F30/398 ,  H01L27/0207 ,  G06F2111/04

Abstract: A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells.