公开(公告)号：US20200091084A1

公开(公告)日：2020-03-19

申请号：US16689628

申请日：2019-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-woo KIM ,  Joon-sung LIM ,  Jang-gn YUN ,  Sung-min HWANG

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

公开(公告)号：US20150011064A1

公开(公告)日：2015-01-08

申请号：US14495397

申请日：2014-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-min HWANG ,  Han-soo KIM ,  Won-seok CHO ,  Jae-hoon JANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/306 ,  H01L21/285 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract translation: 提供了具有金属源线的垂直非易失性存储器件。 垂直非易失性存储器件包括形成在半导体衬底的第一部分上且相对于半导体衬底的表面垂直布置的单元串单元，形成在半导体衬底的第二部分之间的细胞串单元 在杂质区上形成的导电线，以及形成在电池串单元的侧壁上的间隔物，并使导电线与电池串单元绝缘。