公开(公告)号：US20190189592A1

公开(公告)日：2019-06-20

申请号：US16105202

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hoon SON ,  Jung-Hwan CHOI ,  Seok-Hun HYUN

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L2224/02379 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1434

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

公开(公告)号：US20220310151A1

公开(公告)日：2022-09-29

申请号：US17807163

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik MOON ,  Gil-Hoon CHA ,  Ki-Seonk OH ,  Chang-Kyo LEE ,  Yeon-Kyu CHOI ,  Jung-Hwan CHOI ,  Kyung-Soo HA ,  Seok-Hun HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.