公开(公告)号：US11791314B2

公开(公告)日：2023-10-17

申请号：US17467860

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seoeun Kyung ,  Inhee Yoo

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/49176 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83203 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2924/182 ,  H01L2924/1815

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.

公开(公告)号：US20240006282A1

公开(公告)日：2024-01-04

申请号：US18345955

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim ,  Seoeun Kyung

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49822 ,  H01L24/08 ,  H01L2924/1715 ,  H01L2224/08235

Abstract: A semiconductor package includes: a redistribution structure having a first surface and a second surface and including a plurality of redistribution layers, the plurality of redistribution layers including first and second redistribution layers adjacent to the first and second surfaces, respectively,; a semiconductor chip disposed on the first surface; a frame including a wiring structure connected to a first redistribution via of the first redistribution layer; and UBM layers disposed on the second surface and having a plurality of UBM vias. The UBM layers may include at least one UBM layer overlapping the first redistribution via, and the first redistribution via may be disposed so as not to overlap a plurality of UBM vias of the at least one UBM layer and to overlap an internal region closer to a central point of the at least one UBM layer than the plurality of UBM vias.

公开(公告)号：US20220149010A1

公开(公告)日：2022-05-12

申请号：US17467860

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seoeun Kyung ,  Inhee Yoo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.