公开(公告)号：US20150311310A1

公开(公告)日：2015-10-29

申请号：US14700346

申请日：2015-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKJUN WON ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。