公开(公告)号：US20180067847A1

公开(公告)日：2018-03-08

申请号：US15695060

申请日：2017-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOONNA OH ,  DEOK-GU YOON ,  SANGUHN CHA

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0207 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/12 ,  G11C8/12 ,  G11C29/42 ,  G11C29/76 ,  G11C2029/1204 ,  G11C2029/4402

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.

公开(公告)号：US20210224156A1

公开(公告)日：2021-07-22

申请号：US16926000

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHYE CHO ,  KIJUN LEE ,  YEONGGEOL SONG ,  SUNGRAE KIM ,  CHANKI KIM ,  MYUNGKYU LEE ,  SANGUHN CHA

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00

Abstract: An error correction circuit of a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.

公开(公告)号：US20210208967A1

公开(公告)日：2021-07-08

申请号：US16988931

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGUHN CHA ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15 ,  H03M13/11

Abstract: A memory controller controls a memory module including data chips and first and second parity chips. The memory controller includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder receives error information signals associated with the data chips, performs an ECC decoding on a codeword set from the memory module using the parity check matrix to generate a first syndrome and a second syndrome, and corrects bit errors in a user data set based on the error information signals and the second syndrome. The bit errors are generated by a row fault and uncorrectable using the first syndrome and the second syndrome. Each of the error information signals includes row fault information indicating whether the row fault occurs in at least one of memory cell rows in corresponding one of the data chips.

公开(公告)号：US20190179699A1

公开(公告)日：2019-06-13

申请号：US16024941

申请日：2018-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEJEONG HONG ,  SANGUHN CHA

IPC: G06F11/10 ,  G06F3/06 ,  G11C7/10 ,  H03M13/09

Abstract: A memory system includes a memory device and a memory controller. The memory device outputs data in response to a read command. The memory device includes a first function circuit which performs a first operation based on data stored in the memory device, in response to the read command, to generate first processed data. The memory controller provides the read command to the memory device in response to a read request received from a host. The memory controller receives status information associated with performing the first operation. The memory controller includes a second function circuit which performs a second operation based on the first processed data to generate second processed data. A manner of the second operation varies based on the status information.