公开(公告)号：US10025345B2

公开(公告)日：2018-07-17

申请号：US15285633

申请日：2016-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Jae Jeon ,  Gyeong Han Cha

IPC: G06F9/00 ,  G06F1/12 ,  G06F1/10 ,  H04L7/00

Abstract: A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.