公开(公告)号：US20190146870A1

公开(公告)日：2019-05-16

申请号：US16023835

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn CHA ,  Myeong-O KIM ,  In-Woo JUN

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G06F3/06

Abstract: Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.

公开(公告)号：US20190012229A1

公开(公告)日：2019-01-10

申请号：US15870220

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO ., LTD .

Inventor： SANG-UHN CHA ,  Myeong-O KIM

IPC: G06F11/10 ,  G11C29/52

Abstract: An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from. the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.

公开(公告)号：US20160071561A1

公开(公告)日：2016-03-10

申请号：US14801707

申请日：2015-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Yoon LEE ,  Myeong-O KIM ,  Kyo-Min SOHN ,  Sang-Joon HWANG

IPC: G11C7/12 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.

Abstract translation: 存储器件可以包括预充电控制电路，有源控制电路和驱动器电路。 预充电控制电路可以被配置为在接收到用于第一组的预充电命令之后接收有效命令，确定在接收到活动命令时第一组的预充电操作是否已经结束，并且生成 根据确定的结果激活指令信号。 有源控制电路可以被配置为根据有效指令信号产生用于有效操作的有效控制信号。 驱动器电路可以被配置为根据主动控制信号来控制有效操作。