公开(公告)号：US20220399463A1

公开(公告)日：2022-12-15

申请号：US17724619

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Doyoung CHOI ,  Daewon HA ,  Mingyu KIM

IPC: H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a plurality of source/drain patterns in a first direction on the active pattern, a first channel structure between a pair of source/drain patterns, a second channel structure between another pair of source/drain patterns, a first gate electrode extending in a second direction perpendicular to the first direction, and a second gate electrode intersecting the second channel structure and extending in the second direction. The first gate electrode includes a first portion between a bottom surface of the first channel structure and a top surface of the active pattern, and the second gate electrode includes a first portion between a bottom surface of the second channel structure and the top surface of the active pattern. A thickness of the first portion of the second gate electrode is greater than a thickness of the first portion of the first gate electrode.

公开(公告)号：US20220109057A1

公开(公告)日：2022-04-07

申请号：US17245601

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Myung Gil KANG ,  Wandon KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US20240030304A1

公开(公告)日：2024-01-25

申请号：US18478373

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Myung Gil KANG ,  Wandon KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42364 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/78696

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US20200235222A1

公开(公告)日：2020-07-23

申请号：US16836138

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwoo NOH ,  Munhyeon KIM ,  Hansu OH ,  Sungman WHANG ,  Dongwon KIM

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.