公开(公告)号：US20130240959A1

公开(公告)日：2013-09-19

申请号：US13716402

申请日：2012-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsup LEE ,  Yoonho SON ,  Woogwan SHIM ,  Chan Min LEE ,  Inseak HWANG

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离图案限定的有源图案，与有源图案交叉的栅极电极，栅电极两侧的有源图案中的第一杂质区域和第二杂质区域，位线 跨越栅电极，将第一杂质区与位线电连接的第一接触和第一接触的下侧表面上的第一氮化物图案。 垂直于位线的延伸方向测量的第一接触件的宽度可以基本上等于位线的宽度。

公开(公告)号：US20160049407A1

公开(公告)日：2016-02-18

申请号：US14803217

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonho SON ,  Mongsup LEE

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/768 ,  H01L29/06 ,  H01L21/3213

CPC classification number: H01L27/10876 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/76801 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a device isolation pattern on a substrate to define active patterns, a gate electrode crossing the active patterns, first and second impurity regions in each of the active patterns and on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region to the bit line, and a second contact electrically connected to the second impurity region. The second contact includes a vertically-extended portion covering an upper side surface of the second impurity region.

Abstract translation: 半导体器件包括在衬底上的器件隔离图案，以限定有源图案，与有源图案交叉的栅极电极，每个有源图案中的栅极电极和栅电极两侧的第一和第二杂质区域，与栅极交叉的位线 电极，将第一杂质区电连接到位线的第一接触点和与第二杂质区域电连接的第二接触点。 第二触点包括覆盖第二杂质区域的上侧表面的垂直延伸部分。