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    MEMORY DEVICE INCLUDING PLURALITY OF LATCHES AND SYSTEM ON CHIP INCLUDING THE SAME
    2.
    发明申请
    MEMORY DEVICE INCLUDING PLURALITY OF LATCHES AND SYSTEM ON CHIP INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190311751A1

    公开(公告)日：2019-10-10

    申请号：US16375201

    申请日：2019-04-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-shin YOO ,  Min-su KIM ,  Hyun-chul HWANG

    IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G06F3/06

    Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

    CLOCK GATING CIRCUIT
    3.
    发明申请
    CLOCK GATING CIRCUIT 审中-公开

    公开(公告)号：US20190173472A1

    公开(公告)日：2019-06-06

    申请号：US16259631

    申请日：2019-01-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ah-Reum KIM ,  Hyun LEE ,  Min-su KIM

    IPC: H03K19/0185 ,  H03K3/356 ,  H03K3/037 ,  H03K19/00 ,  H03K3/012

    CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

    MEMORY DEVICE INCLUDING PLURALITY OF LATCHES AND SYSTEM ON CHIP INCLUDING THE SAME
    4.
    发明申请
    MEMORY DEVICE INCLUDING PLURALITY OF LATCHES AND SYSTEM ON CHIP INCLUDING THE SAME 有权

    公开(公告)号：US20210158847A1

    公开(公告)日：2021-05-27

    申请号：US17104592

    申请日：2020-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-shin YOO ,  Min-su KIM ,  Hyun-chul HWANG

    IPC: G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G11C8/10

    Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

    SEMICONDUCTOR CIRCUIT AND METHOD FOR OPERATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR CIRCUIT AND METHOD FOR OPERATING THE SAME 审中-公开
    半导体电路及其操作方法

    公开(公告)号：US20140184288A1

    公开(公告)日：2014-07-03

    申请号：US14132111

    申请日：2013-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chung-Hee KIM ,  Ju-Hyun KANG ,  Dong-Youb KIM ,  Min-su KIM ,  Sun-Gyeum KIM ,  Uk-Rae CHO ,  Sang-Shin HAN

    IPC: H03L7/00

    CPC classification number: G06F1/12

    Abstract: Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively.

    Abstract translation: 提供一种半导体电路及其操作方法。 半导体电路包括：第一触发器，被配置为基于与第一时钟同步的输入数据，输出与第一时钟不同的第二时钟同步的第一输出数据;以及第二触发器，被配置为基于第一触发器 输出数据，输出与第二时钟同步的第二输出数据，其中第一和第二触发器分别共享反相的第二时钟和延迟的第二时钟，并且基于此输出第一和第二输出数据。

    INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING AND DESIGNING THE SAME
    7.
    发明申请
    INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING AND DESIGNING THE SAME 审中-公开

    公开(公告)号：US20200185375A1

    公开(公告)日：2020-06-11

    申请号：US16506389

    申请日：2019-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min-su KIM

    IPC: H01L27/02 ,  H01L23/00

    Abstract: Provided is an integrated circuit including a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, where the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the second direction. The plurality of metal lines are formed in a conduction layer above the gate layer, where the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit wiring structure where N is a positive integer and a plurality of unit wiring structures are arranged in the first direction. Design efficiency and performance of the integrated circuit are enhanced through the unit wiring structure.

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