公开(公告)号：US20160163248A1

公开(公告)日：2016-06-09

申请号：US14796808

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HO YANG ,  Miaofeng Wang ,  Ho Seok Shin

IPC: G09G3/20

CPC classification number: G09G5/003 ,  G09G2320/066 ,  G09G2330/021 ,  G09G2360/144

Abstract: A display controller includes a local contrast enhancement circuit that includes a plurality of scale circuits. Each scale circuit includes a block separation circuit configured to divide input display data into sub blocks, a calculation circuit configured to calculate a feature value that characterizes each of the sub blocks, and a storage device configured to store the feature value. The number and size of the sub blocks differ among the scale circuits.

Abstract translation: 显示控制器包括包括多个刻度电路的局部对比度增强电路。 每个缩放电路包括块分离电路，其被配置为将输入显示数据划分为子块，计算电路，被配置为计算表征每个子块的特征值;以及存储装置，被配置为存储特征值。 子块的数量和大小在缩放电路之间不同。

公开(公告)号：US09922616B2

公开(公告)日：2018-03-20

申请号：US14796808

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Yang ,  Miaofeng Wang ,  Ho Seok Shin

IPC: G09G5/10 ,  G09G5/00

CPC classification number: G09G5/003 ,  G09G2320/066 ,  G09G2330/021 ,  G09G2360/144

Abstract: A display controller includes a local contrast enhancement circuit that includes a plurality of scale circuits. Each scale circuit includes a block separation circuit configured to divide input display data into sub blocks, a calculation circuit configured to calculate a feature value that characterizes each of the sub blocks, and a storage device configured to store the feature value. The number and size of the sub blocks differ among the scale circuits.

公开(公告)号：US20140071143A1

公开(公告)日：2014-03-13

申请号：US14026478

申请日：2013-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Miaofeng Wang ,  Yoon Hak Kim ,  Sumit Srivastava

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G09G3/3648 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2340/02 ,  G09G2340/16 ,  H04N19/102 ,  H04N19/124 ,  H04N19/137 ,  H04N19/14 ,  H04N19/152 ,  H04N19/186 ,  H04N19/427 ,  H04N19/436 ,  H04N19/70 ,  H04N19/85

Abstract: An image compression circuit includes an encoder configured to compress a current frame and to output current frame compressed data and a current frame bitstream; a decoder configured to decode the previous frame bitstream and to output previous frame compressed data; a frame memory controller configured to write the current frame bitstream to a frame memory and simultaneously read a previous frame bitstream from the frame memory; a dynamic capacitance compensation controller configured to output a previous frame reference value based on the current frame, the current frame compressed data, and the previous frame compressed data; and an overdrive circuit configured to generate a current overdriven frame including an overdrive pixel value for a current pixel based on a pixel value of the current pixel in the current frame and the previous frame reference value.

Abstract translation: 图像压缩电路包括被配置为压缩当前帧并输出当前帧压缩数据和当前帧比特流的编码器; 解码器，被配置为对先前帧比特流进行解码并输出先前的帧压缩数据; 帧存储器控制器，被配置为将当前帧比特流写入帧存储器并同时从帧存储器读取前一帧比特流; 动态电容补偿控制器，被配置为基于当前帧，当前帧压缩数据和先前帧压缩数据输出先前帧参考值; 以及过驱动电路，被配置为基于当前帧中的当前像素的像素值和前一帧参考值生成包括当前像素的过驱动像素值的电流过驱动帧。