公开(公告)号：US09934830B2

公开(公告)日：2018-04-03

申请号：US15298335

申请日：2016-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Park ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Sungup Moon ,  Kyoyeon Won

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/02

CPC classification number: G11C7/1012 ,  G11C7/02 ,  G11C7/22

Abstract: In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

公开(公告)号：US10366021B2

公开(公告)日：2019-07-30

申请号：US15390063

申请日：2016-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

公开(公告)号：US11023396B2

公开(公告)日：2021-06-01

申请号：US16519487

申请日：2019-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.