公开(公告)号：US09727474B2

公开(公告)日：2017-08-08

申请号：US13966889

申请日：2013-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  INDUSTRY & ACADEMIC COOPERATION GROUP OF SEJONG UNIVERSITY

Inventor： Kwon Taek Kwon ,  Youngsik Kim ,  Woo Chan Park ,  Young Duke Seo ,  Sang Oak Woo ,  Seok Yoon Jung ,  Duk Ki Hong

IPC: G09G5/36 ,  G06F12/0875 ,  G06F12/0855

CPC classification number: G06F12/0875 ,  G06F12/0855

Abstract: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.

公开(公告)号：US09405546B2

公开(公告)日：2016-08-02

申请号：US14199154

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwon Taek Kwon ,  Sang Oak Woo ,  Shi Hwa Lee ,  Seok Yoon Jung

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3859

Abstract: An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.

Abstract translation: 一种用于非阻塞执行静态预定处理器的装置和方法，该装置包括处理器，用于使用传送的输入数据处理至少一个操作，以及用于将输入数据传送到处理器的输入缓冲器， 处理所述至少一个操作，其中所述处理器可以包括执行所述至少一个操作的至少一个功能单元（FU），并且所述至少一个FU可以使用常规等待时间操作和 不规则的延迟操作。

公开(公告)号：US10102005B2

公开(公告)日：2018-10-16

申请号：US15375874

申请日：2016-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwon Taek Kwon ,  Seok Yoon Jung

IPC: G06F9/38 ,  G06F15/76

Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.

公开(公告)号：US20130293543A1

公开(公告)日：2013-11-07

申请号：US13793907

申请日：2013-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Kyu JEONG ,  Jae Don Lee ,  Kwon Taek Kwon ,  Seung Won Lee ,  Shi Hwa Lee

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/80

Abstract: An image processing apparatus. A rendering unit of the image processing apparatus may perform rendering with respect to each of N passes by applying a multi-pass rendering process with respect to an object in an image. The image processing apparatus may include a texture buffer to store information about at least one pixel using second pass rendering different from first pass rendering, while performing the first pass rendering corresponding to a process of generating a final result image among the N passes.

Abstract translation: 一种图像处理装置。 图像处理装置的渲染单元可以通过对图像中的对象应用多遍渲染处理来执行关于N遍中的每一个的渲染。 图像处理装置可以包括纹理缓冲器，以在与N次通过中生成最终结果图像的处理相对应的同时执行与第一遍渲染不同的第二遍渲染来存储关于至少一个像素的信息。