公开(公告)号：US11587947B2

公开(公告)日：2023-02-21

申请号：US17355824

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/1156 ,  H01L23/522 ,  H01L27/1158 ,  H01L23/528

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

公开(公告)号：US11456254B2

公开(公告)日：2022-09-27

申请号：US17027734

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisoo Chung ,  Kang-Won Lee ,  Sung-Min Hwang

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes; a first block and a second block arranged on a first substrate in a first direction, wherein each of the first block and the second block includes electrode layers stacked on the first substrate, a source layer interposed between the first block and the first substrate, and between the second block and the first substrate, a first insulating separation pattern interposed between the first block and the second block and extending in the first direction, wherein the first insulating separation pattern includes a line portion and a protruding portion, the line portion extending in a second direction crossing the first direction, and the protruding portion having a width greater than a width of the line portion, a first source contact plug penetrating the protruding portion of the first insulating separation pattern to electrically connect the source layer, and at least one through via penetrating the source layer and at least one of the first block and the second block.

公开(公告)号：US20210320126A1

公开(公告)日：2021-10-14

申请号：US17355824

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penetrates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

公开(公告)号：US11069706B2

公开(公告)日：2021-07-20

申请号：US16573695

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11556

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.