公开(公告)号：US20230093897A1

公开(公告)日：2023-03-30

申请号：US17707015

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGSOO KIM ,  KYENHEE LEE

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit semiconductor element includes: a substrate; a complementary field effect transistor (FET) (cFET) formed over the substrate and having a quadruple-gate structure, in which nano sheet stacked structures are sequentially stacked; and a planar FET having a mono-gate structure or a zebra fin FET (ZE FINFET) having a triple-gate structure, which are formed over the substrate.

公开(公告)号：US20230189519A1

公开(公告)日：2023-06-15

申请号：US17898816

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINHO KIM ,  KYUNGSOO KIM

IPC: H01L27/11529 ,  H01L27/11 ,  H01L27/11524

CPC classification number: H01L27/11529 ,  H01L27/1116 ,  H01L27/11524

Abstract: A storage device includes a first semiconductor structure having a first cell area, with memory cells disposed on a first semiconductor substrate, and a first metal pad disposed above the first cell area. A second semiconductor structure has a peripheral circuit area on a second semiconductor substrate and on which peripheral circuits are disposed, a second cell area including a plurality of second memory cells, and a second metal pad bonded to the first metal pad. A third semiconductor structure includes a memory controller disposed on a third semiconductor substrate and connected to a third metal pad through a connection via penetrating through the third semiconductor substrate. A connection structure penetrates through the second semiconductor substrate and connects the memory controller to the second semiconductor structure. The memory controller controls the first and second cell areas based on a signal applied from a host through the third metal pad.

公开(公告)号：US20230081783A1

公开(公告)日：2023-03-16

申请号：US17804397

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGSOO KIM ,  JINYOUNG PARK ,  KYEN-HEE LEE

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a gate electrode on a channel pattern connected to the source/drain pattern, an active contact on the source/drain pattern, a first lower interconnection line on the active contact, a second lower interconnection line on the gate electrode, a first spacer between the gate electrode and the active contact, and a second spacer between the first spacer and the gate electrode or the active contact. The gate electrode includes an electrode body portion and an electrode protruding portion protruding from a top surface thereof and contacting the second lower interconnection line. The active contact includes a contact body portion and a contact protruding portion protruding from a top surface thereof and contacting the first lower interconnection line. A top surface of the first spacer is higher than a top surface of the second spacer.