公开(公告)号：US20200161330A1

公开(公告)日：2020-05-21

申请号：US16750176

申请日：2020-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KOHJI KANAMORI ,  SEO-GOO KANG ,  YOUNGHWAN SON ,  KWONSOON JO

IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.