公开(公告)号：US20150234452A1

公开(公告)日：2015-08-20

申请号：US14590504

申请日：2015-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun HEO ,  Jong-Pil LEE

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G05F1/10 ,  G05F3/02 ,  G06F1/26 ,  H02M3/158 ,  H02M3/33507 ,  H02M3/33561 ,  H02M2001/0032 ,  H02M2001/0045 ,  H02M2001/009 ,  Y02B70/16 ,  Y02D10/172

Abstract: Provided is a power management device which includes a first regulator, a second regulator and a control register unit. The first regulator provides a first driving voltage to a first power domain of an application processor. The second regulator provides a second power domain of the application processor with a second driving voltage having a correlation with the first driving voltage. The control register unit controls, in response to a command from the application processor, a reference voltage generation circuit that provides a first reference voltage and a second reference voltage to the first regulator and the second regulator, respectively. The level of the first driving voltage is maintained in a first driving mode. The first driving voltage and the second driving voltage have a set voltage difference in a second driving mode.

Abstract translation: 提供了一种电力管理装置，其包括第一调节器，第二调节器和控制寄存器单元。 第一调节器向应用处理器的第一电源域提供第一驱动电压。 第二调节器提供具有与第一驱动电压相关的第二驱动电压的应用处理器的第二电源域。 控制寄存器单元响应于来自应用处理器的命令控制分别向第一调节器和第二调节器提供第一参考电压和第二参考电压的参考电压产生电路。 第一驱动电压的电平保持在第一驱动模式。 第一驱动电压和第二驱动电压在第二驱动模式下具有设定的电压差。

公开(公告)号：US20210223847A1

公开(公告)日：2021-07-22

申请号：US17222364

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sang JUNG ,  Sang-Wook JU ,  Jung-Hun HEO

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/46

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.

公开(公告)号：US20190187769A1

公开(公告)日：2019-06-20

申请号：US16284698

申请日：2019-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sang JUNG ,  Sang-Wook JU ,  Jung-Hun HEO

IPC: G06F1/324 ,  G06F9/46 ,  G06F1/3287 ,  G06F1/3234

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D50/20

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.

公开(公告)号：US20160162001A1

公开(公告)日：2016-06-09

申请号：US14959824

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sang JUNG ,  Sang-Wook JU ,  Jung-Hun HEO

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D50/20

Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.

Abstract translation: 描述了用于芯片系统（SoC）的电源管理的系统，装置和方法。 在一种方法中，监视SoC的核/处理器的操作状态，并且如果核/处理器处于空闲或待机模式，则驱动与诸如存储器接口相关联的组件（例如存储器接口）的时钟信号的速率 空闲的核心/处理器减少，从而降低功耗。