公开(公告)号：US20160162001A1

公开(公告)日：2016-06-09

申请号：US14959824

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sang JUNG ,  Sang-Wook JU ,  Jung-Hun HEO

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D50/20

Abstract: Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.

Abstract translation: 描述了用于芯片系统（SoC）的电源管理的系统，装置和方法。 在一种方法中，监视SoC的核/处理器的操作状态，并且如果核/处理器处于空闲或待机模式，则驱动与诸如存储器接口相关联的组件（例如存储器接口）的时钟信号的速率 空闲的核心/处理器减少，从而降低功耗。

公开(公告)号：US20210223847A1

公开(公告)日：2021-07-22

申请号：US17222364

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sang JUNG ,  Sang-Wook JU ,  Jung-Hun HEO

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/46

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.

公开(公告)号：US20190187769A1

公开(公告)日：2019-06-20

申请号：US16284698

申请日：2019-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sang JUNG ,  Sang-Wook JU ,  Jung-Hun HEO

IPC: G06F1/324 ,  G06F9/46 ,  G06F1/3287 ,  G06F1/3234

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/46 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D50/20

Abstract: System on chip including plurality of processors including first and second processors; plurality of intellectual properties (IPs) including first and second IPs; memory interface; internal clock circuit to receive reference clock signal, generate first internal clock signal, and provide first internal clock signal to first IP; memory interface clock circuit to receive reference clock signal, generate memory interface clock signal, and provide memory interface clock signal to memory interface; and power management unit (PMU), wherein first internal clock signal drives first IP, memory interface clock signal drives memory interface, PMU generates first control signal based on operational states of plurality of processors, and provides first control signal to internal clock circuit, PMU generates second control signal based on operational states of plurality of processors, and provides second control signal to memory interface clock circuit, internal clock circuit sets clock rate of first internal clock signal based on first control signal, and memory interface clock circuit sets clock rate of memory interface clock signal based on second control signal.