公开(公告)号：US20190386024A1

公开(公告)日：2019-12-19

申请号：US16555113

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Suk LEE ,  Hong-Suk KIM ,  Jae-Young AHN ,  Han-Jin LIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.