-
公开(公告)号:US20240153906A1
公开(公告)日:2024-05-09
申请号:US18386687
申请日:2023-11-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Byeongtak PARK , Gwanghee JO , Siwoong WOO , Jiwon SON , Yongjoo LEE , Hoechul KIM , Inhwa BAEK , Seungdae SEOK , Sehoon JANG , Jaehyun PHEE
IPC: H01L23/00
CPC classification number: H01L24/74 , H01L2224/74 , H01L2924/40
Abstract: A substrate bonding apparatus includes a first bonding chuck having a first base, a deformable plate on the first base to support a first substrate, and a lower pressurer under the first base to apply pressure to the deformable plate, and a second bonding chuck vertically spaced apart from the first bonding chuck and having a second base to fix a second substrate, and an upper pressurer to apply pressure to the second substrate. The deformable plate includes an outer portion surrounding a center portion, a bottom surface of the outer portion of the deformable plate being adhered to the first base, the center portion being deformable in the vertical direction by the lower pressurer, and thicknesses of the center and outer portions of the deformable plate in the vertical direction being different from each other.
-
公开(公告)号:US20230079198A1
公开(公告)日:2023-03-16
申请号:US17898416
申请日:2022-08-29
Inventor: Younhee LIM , Sangyeon PAK , Jiwon SON , Yong Wan JIN , SeungNam CHA , Kyungbae PARK , Chuljoon HEO
Abstract: A transparent conductive film includes a metal chalcogenide compound doped with a halogen and having a sheet resistance at room temperature of less than or equal to about 60 ohm/sq.
-
公开(公告)号:US20250140568A1
公开(公告)日:2025-05-01
申请号:US18640322
申请日:2024-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SangHyuk YOO , Songyun KANG , Jiwon SON
IPC: H01L21/3115 , H01L21/02 , H01L21/311
Abstract: The present disclosure relates to methods of manufacturing semiconductor devices, and a method for manufacturing a semiconductor device according to an embodiment comprises: forming an insulating layer including a silicon compound on a substrate; forming a trench by recessing a portion of the insulating layer toward the substrate, wherein the trench is adjacent a first portion of the insulating layer and a second portion of the insulating layer; implanting a first impurity with a first concentration in the first portion of the insulating layer; implanting a second impurity with a second concentration in the second portion of the insulating layer, wherein the implanting the first impurity and the implanting the second impurity are performed simultaneously; and etching the first portion of the insulating layer after the implanting the first impurity, wherein the first impurity and the second impurity each include at least one of boron and arsenic.
-
-