公开(公告)号：US10355010B2

公开(公告)日：2019-07-16

申请号：US15295119

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Hyun You ,  Jin Taek Park ,  Taek Soo Shin ,  Sung Yun Lee

IPC: H01L29/788 ,  H01L29/792 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

公开(公告)号：US10854623B2

公开(公告)日：2020-12-01

申请号：US16509708

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Hyun You ,  Jin Taek Park ,  Taek Soo Shin ,  Sung Yun Lee

IPC: H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.