公开(公告)号：US20240186409A1

公开(公告)日：2024-06-06

申请号：US18372325

申请日：2023-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyeol MAENG ,  Hyungjin Lee ,  Huichul Shin

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0649 ,  H01L29/7851

Abstract: An integrated circuit device includes: a semiconductor substrate; first and second conductivity type wells formed in the semiconductor substrate; a source region formed in the second conductivity type well; a drain region formed in the first conductivity type well; a recess insulating layer disposed between the source region and the drain region, and including an upper insulating unit and a lower insulating unit, wherein the upper insulating unit fills an upper substrate recess that extends from an upper surface of the first conductivity type well, and wherein the lower insulating unit fills a lower substrate recess that extends from the upper substrate recess; and a gate electrode layer arranged on the first and second conductivity type wells, and wherein the recess insulating layer has a shape in which both sides thereof are asymmetric with respect to a center of the upper insulating unit.

公开(公告)号：US11908807B2

公开(公告)日：2024-02-20

申请号：US17574212

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huichul Shin ,  Hyungjin Lee ,  Jinhong Park ,  Mingeun Song ,  Euiyoung Jeong ,  Hiroki Fujii

IPC: H01L23/552 ,  H01L21/82 ,  H01L21/78

CPC classification number: H01L23/552

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate with first-conductivity-type impurities; first and second active regions provided on the substrate; a first deep element isolation layer surrounding the first active region; a second deep element isolation layer surrounding the second active region; a suction region surrounding the first and second deep element isolation layers, the suction region including the first-conductivity-type impurities; a well region provided in the substrate between the first and second active regions, the well region including second-conductivity-type impurities different from the first-conductivity-type impurities; a shallow element isolation layer provided between the suction region and the well region; and a guard structure connected to the suction region. The substrate includes a signal path portion that is provided between a top surface of the substrate and the well region, and surrounds an upper portion of the well region.

公开(公告)号：US20230261106A1

公开(公告)日：2023-08-17

申请号：US18092246

申请日：2022-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyeol Maeng ,  Hyungjin Lee ,  Huichul Shin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0878 ,  H01L29/4966 ,  H01L29/7851 ,  H01L21/26513 ,  H01L21/28088 ,  H01L29/66545 ,  H01L29/66681

Abstract: A transistor includes a substrate including a P-type-sub region doped with P-type impurities, a well region positioned at an upper portion of the substrate and doped with P-type impurities, a gate structure on the well region, and drain and source regions. The gate structure includes a gate insulation layer, first and second conductive patterns for adjusting a threshold voltage and a gate electrode. The drain and source regions are positioned at an upper portion of the substrate adjacent first and second sidewalk of the gate structure, respectively. The source region is doped with N-type impurities. The drain region includes a highly doped N-type impurity region, an N-type impurity region, and a lightly doped P-type impurity region sequentially disposed in a downward direction from a top surface of the substrate. A boundary between the well region and the P-type sub region is positioned under a bottom of the drain region.