公开(公告)号：US10665574B2

公开(公告)日：2020-05-26

申请号：US16056709

申请日：2018-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok Im ,  Kyoung-Min Lee ,  Kyungsoo Lee ,  Horang Jang

IPC: H01L23/367 ,  H01L23/42 ,  H01L25/10 ,  H01L23/498 ,  H01L23/552 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.

公开(公告)号：US10133692B2

公开(公告)日：2018-11-20

申请号：US15190629

申请日：2016-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho Huh ,  Horang Jang ,  Tomas Scherrer ,  Jaewon Lee

IPC: G06F13/16 ,  G06F13/36 ,  G06F13/42 ,  G11C8/10 ,  G11C7/10 ,  G11C7/22

Abstract: A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.

公开(公告)号：US12034373B2

公开(公告)日：2024-07-09

申请号：US17575249

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook Park ,  Joonseok Park ,  Jongjin Lee ,  Horang Jang

IPC: H02M3/158 ,  G06F13/42 ,  H02M3/157

CPC classification number: H02M3/1584 ,  G06F13/4282 ,  H02M3/157 ,  G06F2213/0016 ,  G06F2213/0038

Abstract: An electronic device includes a system on chip (SoC) and a power management integrated circuit (PMIC). The SoC includes a plurality of power domains and a dynamic voltage and frequency scaling (DVFS) controller which performs DVFS on the power domains The PMIC includes direct current (DC)-DC converters and a control logic which controls the plurality of DC-DC converters, and each of the DC-DC converters provides a corresponding output voltage to a respective one of the power domains. The control logic designates a target DC-DC converter which provides a target output voltage having a target level as a global DC-DC converter and provides the target output voltage to a power domain corresponding the global DC-DC converter and to at least one first power domain consuming the target output voltage, from among the plurality of power domains, by sharing the target output voltage provided by the global DC-DC converter.

公开(公告)号：US11037913B2

公开(公告)日：2021-06-15

申请号：US16854971

申请日：2020-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok Im ,  Kyoung-Min Lee ,  Kyungsoo Lee ,  Horang Jang

IPC: H01L25/10 ,  H01L23/367 ,  H01L23/498 ,  H01L23/42 ,  H01L23/552 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.