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公开(公告)号:US12046193B2
公开(公告)日:2024-07-23
申请号:US17835756
申请日:2022-06-08
发明人: Hoonmo Yang , Sungchul Yoon
IPC分类号: G09G3/30 , G09G3/3225 , G09G3/36 , G09G5/39
CPC分类号: G09G3/3225 , G09G5/39 , G09G2330/021 , G09G2340/0435 , G09G2360/18
摘要: An application processor includes a main processor and a display controller controlled by the main processor. The display controller controls a display device that is located outside the application processor and operates based on a variable frame rate scheme, receives an event signal associated with a frame update of the display device, adjusts a frame rate of the display device based on the event signal, records timing information associated with the frame update of the display device based on the event signal, and provides the timing information to the main processor.
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2.
公开(公告)号:US11817050B2
公开(公告)日:2023-11-14
申请号:US18065906
申请日:2022-12-14
发明人: Changju Lee , Yonjun Shin , Hoonmo Yang , Sungchul Yoon , Junghak Lee
IPC分类号: G09G3/3225
CPC分类号: G09G3/3225 , G09G2310/0243 , G09G2310/0278 , G09G2310/08 , G09G2320/0247 , G09G2330/021
摘要: A display system including a host processor and a display driver integrated circuit may be provided. The host processor may generate a clock signal that swings swinging between a high level and a low level, generate and output a first synchronization signal based on the clock signal, generate a wakeup interrupt by measuring a frame update period of a display panel, generates frame data based on the first synchronization signal by enabling an image providing path based on the wakeup interrupt, and output the frame data for every frame update period. The display driver integrated circuit may receive the first synchronization signal and the frame data from the host processor, and control the display panel such that a frame image corresponding to the frame data is displayed on the display panel based on the first synchronization signal without storing the frame data.
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公开(公告)号:US11694617B2
公开(公告)日:2023-07-04
申请号:US17215507
申请日:2021-03-29
发明人: Sungchul Yoon , Inyup Kang , Hoonmo Yang , Kyungah Jeong
IPC分类号: G09G3/3233 , G09G3/20
CPC分类号: G09G3/3233 , G09G3/2003 , G09G2320/0666 , G09G2340/06 , G09G2340/10 , G09G2340/12
摘要: An image processing device includes a blender and a display quality enhancer. The blender is configured to receive a plurality of layer data, generate first image data by blending the plurality of layer data, the first image data including a plurality of pixel values corresponding to a screen in a display device, and generate pixel map data including a plurality of pixel identifications (IDs) based on the plurality of layer data, the plurality of layer data representing a plurality of images to be displayed on the screen, the plurality of pixel IDs indicating display quality enhancement algorithms to be applied to the plurality of pixel values. The display quality enhancer is configured to generate second image data including a plurality of display quality enhancement pixel values by applying the display quality enhancement algorithms to the plurality of pixel values based on the first image data and the pixel map data.
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4.
公开(公告)号:US20230110768A1
公开(公告)日:2023-04-13
申请号:US18065906
申请日:2022-12-14
发明人: Changju Lee , Yonjun Shin , Hoonmo Yang , Sungchul Yoon , Junghak Lee
IPC分类号: G09G3/3225
摘要: A display system including a host processor and a display driver integrated circuit may be provided. The host processor may generate a clock signal that swings swinging between a high level and a low level, generate and output a first synchronization signal based on the clock signal, generate a wakeup interrupt by measuring a frame update period of a display panel, generates frame data based on the first synchronization signal by enabling an image providing path based on the wakeup interrupt, and output the frame data for every frame update period. The display driver integrated circuit may receive the first synchronization signal and the frame data from the host processor, and control the display panel such that a frame image corresponding to the frame data is displayed on the display panel based on the first synchronization signal without storing the frame data.
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5.
公开(公告)号:US11532269B2
公开(公告)日:2022-12-20
申请号:US17381788
申请日:2021-07-21
发明人: Changju Lee , Yonjun Shin , Hoonmo Yang , Sungchul Yoon , Junghak Lee
IPC分类号: G09G3/3225
摘要: A display system including a host processor and a display driver integrated circuit may be provided. The host processor may generate a clock signal that swings swinging between a high level and a low level, generate and output a first synchronization signal based on the clock signal, generate a wakeup interrupt by measuring a frame update period of a display panel, generates frame data based on the first synchronization signal by enabling an image providing path based on the wakeup interrupt, and output the frame data for every frame update period. The display driver integrated circuit may receive the first synchronization signal and the frame data from the host processor, and control the display panel such that a frame image corresponding to the frame data is displayed on the display panel based on the first synchronization signal without storing the frame data.
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