公开(公告)号：US20240224544A1

公开(公告)日：2024-07-04

申请号：US18512199

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIHONG JEONG ,  Sangsub SONG ,  Heewoo AN

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A processor chip for a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface and mounted on a package substrate, and a plurality of chip pads disposed on the first surface of the substrate and electrically connected to the package substrate, wherein the first surface is divided into a first area and a second area, the first area includes four sides of the first surface and the second area includes a center of the first surface, and the plurality of chip pads are located on the first area and are arranged on at least a portion of a side of the first surface in a line along the side.

公开(公告)号：US20240113074A1

公开(公告)日：2024-04-04

申请号：US18374437

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heewoo AN ,  Sangsub SONG ,  Kihong JEONG

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: Provided is a semiconductor package including a first substrate having an upper surface and a lower surface, and including a substrate pad arranged on the upper surface, a first chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of first chips offset-stacked in a first direction, a lowermost first wire electrically connecting a lowermost first chip to the substrate pad, and a second chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of second chips offset-stacked in the first direction, wherein the second chip stacked structure is spaced apart from the first chip stacked structure with the lowermost first wire therebetween in a horizontal direction, and an upper surface of a lowermost second chip is at a higher vertical direction level than a highest level of the lowermost first wire in a vertical direction.