公开(公告)号：US20250158002A1

公开(公告)日：2025-05-15

申请号：US18939655

申请日：2024-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AE-NEE JANG ,  Haseob SEONG

IPC: H01L25/18 ,  H01L23/00 ,  H10B80/00

Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip may include upper bonding pads in an upper portion thereof, and the second semiconductor chip may include lower bonding pads in a lower portion thereof. The first semiconductor chip and the second semiconductor chip may be connected to each other by the upper bonding pads and the lower bonding pads, which are in direct contact with each other. The upper bonding pads may include a first pad, a dummy pad, and a second pad, which are arranged to be adjacent to each other in a first direction, and the first pads and the second pads are configured to be applied with voltages of different levels from each other.

公开(公告)号：US20250157967A1

公开(公告)日：2025-05-15

申请号：US18941796

申请日：2024-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ae-Nee JANG ,  Haseob SEONG

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip thereon. The first semiconductor chip includes upper bonding pads at an upper portion thereof. The second semiconductor chip includes lower bonding pads at a lower portion thereof. The first semiconductor chip and the second semiconductor chip are connected through direct contact between the upper bonding pads and lower bonding pads. The upper bonding pads include edge bonding pads on an edge region of the first semiconductor chip and arranged in a first direction parallel to an edge of the first semiconductor chip. The edge bonding pads include a first edge pad and a second edge pad disposed adjacent to each other. The each of the first and second edge pads is one of a power pad, a ground pad, and a dummy pad, and the first and second edge pads are of the same type.

公开(公告)号：US20250096218A1

公开(公告)日：2025-03-20

申请号：US18678643

申请日：2024-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haseob SEONG ,  Aenee JANG ,  Dawoon JUNG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor package including: a base structure including upper and lower surfaces with upper and lower connection pads, the upper connection pad being connected to the lower connection pad; a plurality of first semiconductor chips stacked on the base structure, wherein the plurality of first semiconductor chips includes uppermost and lowermost chips, and wherein each of the plurality of first semiconductor chips includes a first lower and upper pads, and a silicon via connecting the first lower and upper pads; a cover chip, on the uppermost semiconductor chip, including an upper surface with a flat region and an edge region; and an upper dummy chip on the flat region and including an area smaller than an area of the cover chip and a thickness greater than a thickness of the cover chip, wherein the first lower pad of the lowermost chip is connected to the upper connection pad, and wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost chip, is connected to the first lower pad of another first semiconductor chip.

公开(公告)号：US20250070048A1

公开(公告)日：2025-02-27

申请号：US18675699

申请日：2024-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dawoon JUNG ,  Haseob SEONG

IPC: H01L23/00 ,  H01L23/28 ,  H01L23/48 ,  H01L25/16 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip including: a first semiconductor substrate having an first active surface and a first inactive surface opposite to the first active surface, and a plurality of first electrodes penetrating through the first semiconductor substrate; a plurality of second semiconductor chips, each of the plurality of second semiconductor chips comprising: a second semiconductor substrate having a second active surface and a second inactive surface opposite to the second active surface, and a plurality of second electrodes penetrating through the second semiconductor substrate, wherein the plurality of second semiconductor chips are stacked on the first semiconductor chip, the second active surfaces of the plurality of second semiconductor substrates face the first inactive surface of the first semiconductor substrate, and vertical heights of the plurality of second semiconductor chips are identical.