公开(公告)号：US20230137339A1

公开(公告)日：2023-05-04

申请号：US17932734

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHO SEO ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  HOYOUNG LEE ,  INSU CHOI

IPC: H03M13/11 ,  G06F3/06 ,  H03M13/00

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US20250060913A1

公开(公告)日：2025-02-20

申请号：US18938050

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHO SEO ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  HOYOUNG LEE ,  INSU CHOI

IPC: G06F3/06 ,  H03M13/00 ,  H03M13/11

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.