公开(公告)号：US20230137339A1

公开(公告)日：2023-05-04

申请号：US17932734

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHO SEO ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  HOYOUNG LEE ,  INSU CHOI

IPC: H03M13/11 ,  G06F3/06 ,  H03M13/00

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US20250060913A1

公开(公告)日：2025-02-20

申请号：US18938050

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHO SEO ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  HOYOUNG LEE ,  INSU CHOI

IPC: G06F3/06 ,  H03M13/00 ,  H03M13/11

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US20240038319A1

公开(公告)日：2024-02-01

申请号：US18222563

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  DEOKHO SEO ,  JAEIN SONG ,  INSU CHOI

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/02

CPC classification number: G11C29/44 ,  G11C29/1201 ,  G11C29/027

Abstract: A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

公开(公告)号：US20220139485A1

公开(公告)日：2022-05-05

申请号：US17388238

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEJEONG KIM ,  NAMHYUNG KIM ,  DOHAN KIM ,  DEOKHO SEO ,  WONJAE SHIN ,  INSU CHOI

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/50

Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.