公开(公告)号：US20250157962A1

公开(公告)日：2025-05-15

申请号：US18761918

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HANSUNG RYU ,  JONGBEOM PARK ,  HASEOB SEONG ,  AE-NEE JANG ,  JEEHYUN JUNG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes: a plurality of first semiconductor chips; a second semiconductor chip including a front surface and disposed on the plurality of first semiconductor chips, and wherein the second semiconductor chip further includes a first dummy pad located on a back surface thereof; and a third semiconductor chip including a front surface and disposed on the second semiconductor chip. The third semiconductor chip further includes a second dummy pad located on the front surface thereof. The first dummy pad is disposed on at least a part of a back surface edge region that is adjacent to a side surface of the second semiconductor chip. The second dummy pad is disposed on at least a part of a front surface edge region that is adjacent to a side surface of the third semiconductor chip. The first dummy pad and the second dummy pad are bonded to each other.

公开(公告)号：US20240055379A1

公开(公告)日：2024-02-15

申请号：US18140960

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HASEOB SEONG ,  AENEE JANG

IPC: H01L23/00 ,  H10B80/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H10B80/00 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L2225/06593 ,  H01L2225/06541 ,  H01L2224/94 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/8013 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08145 ,  H01L2224/0213 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0801 ,  H01L2924/16235 ,  H01L2924/1616

Abstract: A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.