公开(公告)号：US20170012112A1

公开(公告)日：2017-01-12

申请号：US15056033

申请日：2016-02-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JONGYUN KIM ,  WALJUN KIM ,  JUNGHYUN KIM ,  KIWAN AHN

IPC: H01L29/66 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/266

CPC classification number: H01L29/66757 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/32134 ,  H01L27/1288 ,  H01L29/78621 ,  H01L2227/323

Abstract: Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first insulating film is formed on the semiconductor pattern layer. A metal pattern layer including a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode is formed on the first insulating film. A cover layer covering the gate electrode is formed. The first and second alignment electrodes are removed. A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask. The cover layer is removed. A second doping process is performed by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.

Abstract translation: 提供一种制造薄膜晶体管基板的方法，该方法包括在基板上形成半导体图案层。 在半导体图案层上形成第一绝缘膜。 在第一绝缘膜上形成包括栅电极的金属图案层和分别与栅电极的两侧间隔开的第一和第二取向电极。 形成覆盖栅电极的覆盖层。 去除第一和第二对准电极。 通过使用覆盖层作为掩模，通过用第一杂质掺杂半导体图案层来执行第一掺杂工艺。 盖层被去除。 通过使用栅电极作为掩模，通过掺杂具有比第一杂质更低的杂质浓度的第二杂质的半导体图案层来进行第二掺杂工艺。

公开(公告)号：US20170317159A1

公开(公告)日：2017-11-02

申请号：US15583244

申请日：2017-05-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： WALJUN KIM ,  Yeonhong Kim ,  Junghyun Kim ,  Taejin Kim ,  Kiwan Ahn ,  Yongjae Jang

IPC: H01L27/32 ,  H01L27/12

CPC classification number: H01L27/3276 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device including a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer includes a first source region, a first drain region, a second source region, and a second drain region connected to a channel region. The first gate electrode is disposed below the semiconductor layer. The first gate electrode is insulated from the semiconductor layer. The first gate electrode at least partially overlaps the shared channel region. The second gate electrode is disposed above the semiconductor layer. The second gate electrode is insulated by a second gate insulating layer. The second gate electrode at least partially overlaps the channel region.