公开(公告)号：US10101624B2

公开(公告)日：2018-10-16

申请号：US15805957

申请日：2017-11-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seongyeol Syn ,  Jihee Yoon ,  Yonghee Lee ,  Beomjun Kim ,  Jonghwan Lee

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/136

Abstract: A display device includes a gate line; first and second adjacent data lines intersecting the gate line; a first sub-pixel electrode between the first and second data lines; a second sub-pixel electrode between the first gate line and the first sub-pixel electrode; a first switching element connected to the first gate line, the first data line and the first sub-pixel electrode; a second switching element connected to the first gate line, the first data line and the second sub-pixel electrode; a connection electrode connecting the first sub-pixel electrode and the first switching element; a first dummy electrode between the first data line and the second sub-pixel electrode; and a second dummy electrode extending from the connection electrode and is disposed closer to the first data line than the second data line. End portions of the first and second dummy electrodes face each other.

公开(公告)号：US10269321B2

公开(公告)日：2019-04-23

申请号：US15470968

申请日：2017-03-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jihee Yoon ,  Kang-woo Kim ,  Beomjun Kim ,  Jonghwan Lee ,  Hong-woo Lee

IPC: G09G3/36 ,  G09G3/20

Abstract: A display device includes a display panel having a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a plurality of gate signals to the plurality of gate lines, and a data driving circuit configured that outputs a plurality of data signals for driving the plurality of data lines. Each of the plurality of pixels includes a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal among the plurality of gate signals, and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal among the plurality of gate signals. The second gate signal is a signal delayed by a 2×d×H time relative to the first gate signal (where each of d and H is a positive integer, H is a horizontal period, and d×H is a pulse width of first and second gate signals).