公开(公告)号：US20170287425A1

公开(公告)日：2017-10-05

申请号：US15443566

申请日：2017-02-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JAHUN KOO ,  HAKSUN KIM ,  KYUNG-HUN LEE

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3674 ,  G09G3/3688 ,  G09G3/3696 ,  G09G5/18 ,  G09G2300/0417 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/025

Abstract: A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.

公开(公告)号：US20200312262A1

公开(公告)日：2020-10-01

申请号：US16903746

申请日：2020-06-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JAHUN KOO ,  HAKSUN KIM ,  KYUNG-HUN LEE

IPC: G09G3/36 ,  G09G5/18

Abstract: A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.