公开(公告)号：US20250131868A1

公开(公告)日：2025-04-24

申请号：US18917235

申请日：2024-10-16

Applicant: Samsung Display Co., LTD.

Inventor： GICHANG LEE

IPC: G09G3/20

Abstract: A gate driver includes a first transistor including a control electrode, a first electrode receiving a previous signal and a second electrode electrically connected to a Q node, a second transistor including a control electrode electrically connected to the Q node, a first electrode receiving a first voltage and a second electrode electrically connected to a QB node, a third transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the QB node and a second electrode receiving a second voltage, a fourth transistor including a control electrode electrically connected to the QB node, a first electrode receiving the first voltage and a second electrode electrically connected to a GO node and a fifth transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the GO node and a second electrode receiving the second voltage.

公开(公告)号：US20240153424A1

公开(公告)日：2024-05-09

申请号：US18215736

申请日：2023-06-28

Applicant: Samsung Display Co., LTD.

Inventor： KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2330/021 ,  G09G2340/0435

Abstract: A scan driver includes a plurality of stages. Each of the plurality of stages includes a control circuit which controls a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal and a second clock signal, a carry output circuit which outputs a carry signal in response to the voltage of the first node and the voltage of the second node, an enable node controlling circuit which controls a voltage of an enable node in response to the carry signal, an enable signal and an inverted enable signal, a masking circuit which controls a voltage of a third node in response to the voltage of the second node and the voltage of the enable node, and a scan output circuit which outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

公开(公告)号：US20240355269A1

公开(公告)日：2024-10-24

申请号：US18441382

申请日：2024-02-14

Applicant: Samsung Display Co., LTD.

Inventor： KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0426 ,  G09G2310/0267

Abstract: A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode receiving a carry signal, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first enable signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second enable signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode receiving the carry signal, a first electrode connected to the fifth node and a second electrode.

公开(公告)号：US20190212621A1

公开(公告)日：2019-07-11

申请号：US16356548

申请日：2019-03-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： GICHANG LEE ,  INSOO WANG

IPC: G02F1/1362

CPC classification number: G02F1/136213 ,  G02F1/13624 ,  G02F2001/134345

Abstract: A display apparatus includes a gate line, a data line, and a pixel. The pixel includes first and second pixels displaying grayscales different from each other in response to a data voltage provided through the data line. The first pixel includes a first transistor including a gate electrode connected to the gate line and a first terminal connected to the data line and a first liquid crystal capacitor connected to a second terminal of the first transistor. The second pixel includes a second transistor including a gate electrode connected to the gate line and a first terminal connected to the second terminal of the first transistor and a second liquid crystal capacitor connected to a second terminal of the second transistor.

公开(公告)号：US20250148989A1

公开(公告)日：2025-05-08

申请号：US18934395

申请日：2024-11-01

Applicant: Samsung Display Co., LTD.

Inventor： GICHANG LEE

IPC: G09G3/3258 ,  G09G3/32

Abstract: A display device includes: a substrate including a display area and a non-display area; a plurality of data drivers disposed in the display area on the substrate and each including a first latch disposed adjacent to one side of the display area facing the non-display area, a shift register spaced apart from the first latch in a first direction, and a second latch spaced apart from the shift register in the first direction; a plurality of pixels disposed between elements of the data drivers adjacent to each other, where the elements include the first latch, the shift register, and the second latch; and a plurality of first data lines disposed in the non-display area on the substrate, adjacent to the first latch, connected to the data drivers, and to which a data signal in a digital form is applied.

公开(公告)号：US20250140146A1

公开(公告)日：2025-05-01

申请号：US18917416

申请日：2024-10-16

Applicant: Samsung Display Co., LTD.

Inventor： GICHANG LEE

IPC: G09G3/20

Abstract: A gate driver includes a plurality of stages, each including: a first transistor including a first electrode, and a second electrode connected to a first control node; a third transistor including a first electrode connected to the first control node; and a second electrode connected to a second control node; a fifth transistor including a gate electrode connected to an inverting control node, and a second electrode connected to a gate output node; a sixth transistor including a gate electrode connected to the second control node, and a second electrode connected to the gate output node; a seventh transistor including a first electrode, and a second electrode connected to the first control node; and an eighth transistor including a gate electrode to receive an aging signal, a first electrode to receive an aging voltage, and a second electrode connected to the first electrode of the first transistor.

公开(公告)号：US20240386825A1

公开(公告)日：2024-11-21

申请号：US18591991

申请日：2024-02-29

Applicant: Samsung Display Co., LTD.

Inventor： KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/20

Abstract: A gate driver including a plurality of stages. Each of the plurality of stages includes a first masking controlling circuit including a control circuit, a carry output circuit, a first enable node controlling circuit, a first masking circuit, a first gate output circuit, and a second masking controlling circuit including a second enable node controlling circuit, a second masking circuit and a second gate output circuit. The first masking controlling circuit and the second masking controlling circuit shares the control circuit and the carry output circuit.

公开(公告)号：US20240265847A1

公开(公告)日：2024-08-08

申请号：US18369350

申请日：2023-09-18

Applicant: Samsung Display Co., LTD.

Inventor： KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0267 ,  G09G2330/021

Abstract: A scan driver includes: stages. Each stage includes: a first node control circuit for controlling a voltage of a first node; an inverted carry node control circuit for controlling a voltage of an inverted carry node; a carry output circuit for outputting a carry signal; a fourth node control circuit for controlling a voltage of a fourth node in response to the carry signal; a second node control circuit for controlling a voltage of a second node in response to the carry signal, an enable signal, and the voltage of the inverted carry node; a third node control circuit for controlling a voltage of a third node in response to the voltage of the second node and the voltage of the fourth node; and a scan output circuit for outputting a scan signal in response to the voltage of the third node and the voltage of the fourth node.

公开(公告)号：US20250157392A1

公开(公告)日：2025-05-15

申请号：US18825169

申请日：2024-09-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： NAHYEON CHA ,  KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/32

Abstract: A display device includes a display panel driven in units of frames and include a pixel including a pixel driving circuit and a light-emitting element. The pixel driving circuit may include a first driving sub-transistor, a second driving sub-transistor, and a luminance transistor. The first driving sub-transistor includes a first electrode connected to a first node and a gate electrode connected to a second node. The second driving sub-transistor includes a gate electrode connected to the second node. The luminance transistor includes a first electrode connected to the first node, a second electrode connected to a third node, and a gate electrode which receives a luminance signal. The frame may include a first frame and a second frame, and the luminance signal may be activated in the first frame to have a first pulse width and may be activated in the second frame to have a second pulse width.

公开(公告)号：US20240331612A1

公开(公告)日：2024-10-03

申请号：US18395528

申请日：2023-12-23

Applicant: Samsung Display Co., LTD.

Inventor： SANG YONG NO ,  KYUNGHO KIM ,  GICHANG LEE

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2340/0435

Abstract: A display panel includes a first display region to an N-th display region disposed in a row direction. A P-th display region includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal, and a P-th region control circuit including a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, where the first control transistor and the second control transistor are controlled based on a P-th region control signal.