公开(公告)号：US20110035551A1

公开(公告)日：2011-02-10

申请号：US12579931

申请日：2009-10-15

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/30145 ,  G06F9/30043 ,  G06F9/383 ,  G06F12/0862 ,  G06F2212/6028

摘要： A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, each including a prefetch address. The repeat prefetch indirect instruction also includes a count specifying a number of cache lines to be prefetched. The memory address of each of the cache lines is specified by the prefetch address in one of the entries in the prefetch table. A count register, initially loaded with the count specified in the prefetch instruction, stores a remaining count of the cache lines to be prefetched. Control logic fetches the prefetch addresses of the cache lines from the table into the microprocessor and prefetches the cache lines from the system memory into a cache memory of the microprocessor using the count register and the prefetch addresses fetched from the table.

摘要翻译： 微处理器包括用于解码重复预取间接指令的指令解码器，该指令包括用于计算具有多个条目的预取表中的第一条目的地址的地址操作数，每个条目包括预取地址。 重复预取间接指令还包括指定要预取的高速缓存行数的计数。 每个高速缓存行的存储器地址由预取表中的一个条目中的预取地址指定。 最初加载预取指令中指定的计数的计数寄存器存储要预取的高速缓存行的剩余计数。 控制逻辑将缓存行的预取地址从表中提取到微处理器中，并使用计数寄存器和从表中提取的预取地址，将高速缓存行从系统存储器预取到微处理器的高速缓存中。

公开(公告)号：US08762649B2

公开(公告)日：2014-06-24

申请号：US13033765

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/08

CPC分类号： G06F9/3814 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

摘要： A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.

摘要翻译： 具有高速缓冲存储器的微处理器中的数据预取器接收每个存储器块内的地址的存储器访问。 访问地址作为时间的函数是非单调递增或递减的。 当接收到访问时，预取器维护访问的最大地址和最小地址以及对最大和最小地址的更改的计数，并维护由存储器块内的访问地址所牵涉的最近访问的高速缓存行的历史。 预取器还基于计数确定主要的访问方向，并且基于历史确定主要的访问模式。 预取器还根据主要访问模式在主存取方向上预取入高速缓冲存储器，历史指示的存储器块的高速缓存行尚未被最近访问。

公开(公告)号：US08656111B2

公开(公告)日：2014-02-18

申请号：US13033765

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/00

摘要： A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.

公开(公告)号：US08364902B2

公开(公告)日：2013-01-29

申请号：US12579931

申请日：2009-10-15

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/08 ,  G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30043 ,  G06F9/383 ,  G06F12/0862 ,  G06F2212/6028

摘要： A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, each including a prefetch address. The repeat prefetch indirect instruction also includes a count specifying a number of cache lines to be prefetched. The memory address of each of the cache lines is specified by the prefetch address in one of the entries in the prefetch table. A count register, initially loaded with the count specified in the prefetch instruction, stores a remaining count of the cache lines to be prefetched. Control logic fetches the prefetch addresses of the cache lines from the table into the microprocessor and prefetches the cache lines from the system memory into a cache memory of the microprocessor using the count register and the prefetch addresses fetched from the table.

摘要翻译： 微处理器包括用于解码重复预取间接指令的指令解码器，该指令包括用于计算具有多个条目的预取表中的第一条目的地址的地址操作数，每个条目包括预取地址。 重复预取间接指令还包括指定要预取的高速缓存行数的计数。 每个高速缓存行的存储器地址由预取表中的一个条目中的预取地址指定。 最初加载预取指令中指定的计数的计数寄存器存储要预取的高速缓存行的剩余计数。 控制逻辑将缓存行的预取地址从表中提取到微处理器中，并使用计数寄存器和从表中提取的预取地址，将高速缓存行从系统存储器预取到微处理器的高速缓存中。

公开(公告)号：US20110238922A1

公开(公告)日：2011-09-29

申请号：US13033765

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/02

CPC分类号： G06F9/3814 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

摘要： A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.

摘要翻译： 具有高速缓冲存储器的微处理器中的数据预取器接收每个存储器块内的地址的存储器访问。 访问地址作为时间的函数是非单调递增或递减的。 当接收到访问时，预取器维护访问的最大地址和最小地址以及对最大和最小地址的更改的计数，并维护由存储器块内的访问地址所牵涉的最近访问的高速缓存行的历史。 预取器还基于计数确定主要的访问方向，并且基于历史确定主要的访问模式。 预取器还根据主要访问模式在主存取方向上预取入高速缓冲存储器，历史指示的存储器块的高速缓存行尚未被最近访问。

公开(公告)号：US20110238920A1

公开(公告)日：2011-09-29

申请号：US13033848

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/12

CPC分类号： G06F12/0862 ,  G06F9/383 ,  G06F2212/6026

摘要： A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern.

摘要翻译： 微处理器包括高速缓冲存储器和数据预取器。 数据预取器检测第一存储器块内的存储器访问模式，并且基于该模式从第一存储器块预存入高速缓冲存储器高速缓存行。 数据预取器还观察到对第二存储器块的新的存储器访问请求。 数据预取器还确定第一存储器块实际上与第二存储器块相邻，并且当从第一存储器块继续到第二存储器块时，该模式预测对在该存储块内的新请求所涉及的高速缓存行的访问 第二个内存块。 数据预取器还基于该模式从第二存储器块响应地预取到高速缓存存储器高速缓存行。

公开(公告)号：US08719510B2

公开(公告)日：2014-05-06

申请号：US13033848

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/383 ,  G06F2212/6026

摘要： A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern.

摘要翻译： 微处理器包括高速缓冲存储器和数据预取器。 数据预取器检测第一存储器块内的存储器访问模式，并且基于该模式从第一存储器块预存入高速缓冲存储器高速缓存行。 数据预取器还观察到对第二存储器块的新的存储器访问请求。 数据预取器还确定第一存储器块实际上与第二存储器块相邻，并且当从第一存储器块继续到第二存储器块时，该模式预测对在该存储块内的新请求所涉及的高速缓存行的访问 第二个内存块。 数据预取器还基于该模式从第二存储器块响应地预取到高速缓存存储器高速缓存行。

公开(公告)号：US08645631B2

公开(公告)日：2014-02-04

申请号：US13033809

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-level cache memory based on the predominant direction and pattern. The data prefetcher also receives from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line. The data prefetcher also determines one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction. The data prefetcher also causes the one or more cache lines to be prefetched into the first-level cache memory.

摘要翻译： 微处理器包括第一级高速缓冲存储器，二级高速缓冲存储器和数据预取器，该预取器检测呈现给第二级高速缓冲存储器的最近存储器访问的主要方向和模式，并将高速缓存行预取到二级高速缓存 基于主要方向和模式的记忆。 数据预取器还从第一级高速缓冲存储器接收由第一级高速缓存存储器接收的存储器访问的地址，其中该地址涉及高速缓存行。 数据预取器还在主要方向上确定由超过牵涉高速缓存行的模式指示的一个或多个高速缓存行。 数据预取器还使得一个或多个高速缓存行被预取到一级高速缓冲存储器中。

公开(公告)号：US20110238923A1

公开(公告)日：2011-09-29

申请号：US13033809

申请日：2011-02-24

申请人： Rodney E. Hooker ,  John Michael Greer

发明人： Rodney E. Hooker ,  John Michael Greer

IPC分类号： G06F12/02

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-level cache memory based on the predominant direction and pattern. The data prefetcher also receives from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line. The data prefetcher also determines one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction. The data prefetcher also causes the one or more cache lines to be prefetched into the first-level cache memory.

摘要翻译： 微处理器包括第一级高速缓冲存储器，二级高速缓冲存储器和数据预取器，该预取器检测呈现给第二级高速缓冲存储器的最近存储器访问的主要方向和模式，并将高速缓存行预取到二级高速缓存 基于主要方向和模式的记忆。 数据预取器还从第一级高速缓冲存储器接收由第一级高速缓存存储器接收的存储器访问的地址，其中该地址涉及高速缓存行。 数据预取器还在主要方向上确定由超过牵涉高速缓存行的模式指示的一个或多个高速缓存行。 数据预取器还使得一个或多个高速缓存行被预取到一级高速缓冲存储器中。

公开(公告)号：US20110010506A1

公开(公告)日：2011-01-13

申请号：US12573462

申请日：2009-10-05

申请人： John Michael Greer ,  Rodney E. Hooker ,  Albert J. Loper, JR.

发明人： John Michael Greer ,  Rodney E. Hooker ,  Albert J. Loper, JR.

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F2212/6026

摘要： A data prefetcher includes a table of entries to maintain a history of load operations. Each entry stores a tag and a corresponding next stride. The tag comprises a concatenation of first and second strides. The next stride comprises the first stride. The first stride comprises a first cache line address subtracted from a second cache line address. The second stride comprises the second cache line address subtracted from a third cache line address. The first, second and third cache line addresses each comprise a memory address of a cache line implicated by respective first, second and third temporally preceding load operations. Control logic calculates a current stride by subtracting a previous cache line address from a new load cache line address, looks up in the table a concatenation of a previous stride and the current stride, and prefetches a cache line using the hitting table entry next stride.

摘要翻译： 数据预取器包括用于维护加载操作历史的条目表。 每个条目存储标签和相应的下一步。 标签包括第一步和第二步的连接。 第一步是第一步。 第一步包括从第二高速缓存行地址减去的第一高速缓存行地址。 第二步包括从第三高速缓存行地址减去的第二高速缓存行地址。 第一，第二和第三高速缓存行地址各自包括由相应的第一，第二和第三时间上的加载操作牵连的高速缓存行的存储器地址。 控制逻辑通过从新的加载高速缓存行地址中减去先前的高速缓存行地址来计算当前步幅，在表中查找先前步幅和当前步幅的级联，并使用下一步的命中表条目预取高速缓存行。