公开(公告)号：US20170212154A1

公开(公告)日：2017-07-27

申请号：US15401596

申请日：2017-01-09

Applicant: Renesas Electronics Corporation

Inventor： Masanori OTSUKA ,  Wataru SAITO ,  Yoshitaka JINGU ,  Yasuhiko KOKAMI ,  Satoshi KONDO ,  Junya HORISHIMA

IPC: G01R19/32 ,  H03K17/687

CPC classification number: G01R19/32 ,  F16D48/06 ,  F16D2121/18 ,  G01R31/007 ,  H03K17/6872

Abstract: According to one embodiment, a current detection circuit (12) includes: a detection resistor (Rs) provided between a solenoid valve (106) and a solenoid driver (11); an amplification unit (121) configured to amplify a detected voltage of the detection resistor (Rs); an AD converter (122) that is driven by a reference voltage (Vref) generated based on a reference current (Iref) and configured to convert an output voltage from the amplification unit (121) into a digital value and output the digital value as a detected current value (D1); and a correction unit configured to perform a correction on the detected current value (D1). The correction unit includes: a temperature sensor (123); a storage unit (125) configured to store information about temperature characteristics of the detected current value (D1) generated due to temperature characteristics of a reference current in each of two or more different temperature regions; and an operation unit configured to apply, to the detected current value (D1), a first correction coefficient calculated based on a detection result of the temperature sensor (123) and information about temperature characteristics of the detected current value (D1) stored in the storage unit (125).

公开(公告)号：US20160077909A1

公开(公告)日：2016-03-17

申请号：US14953403

申请日：2015-11-29

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki FURUYA ,  Osamu WATANABE ,  Satoshi KONDO

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3234 ,  G06F11/0721 ,  G06F11/079 ,  Y02D50/20

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

公开(公告)号：US20160300653A1

公开(公告)日：2016-10-13

申请号：US15071034

申请日：2016-03-15

Applicant: Renesas Electronics Corporation

Inventor： Satoshi KONDO ,  Kazuaki KUBO ,  Noriyuki ITANO

IPC: H01F7/06 ,  B60R16/02

CPC classification number: H01F7/064 ,  H01F7/1844 ,  H01F2007/1866 ,  H01F2007/1888 ,  H03F3/45475 ,  H03F2203/45588 ,  H03F2203/45594 ,  H03F2203/45616

Abstract: An output driving circuit outputs an output current to a solenoid incorporated in a vehicle through an output terminal. A detection resistor connected between the output terminal and the output driving circuit. An amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor. A current generation circuit configured to output a reference current. A reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current. An A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference. A control circuit configured to control the output current output from the output driving circuit according to the digital detection signal.

Abstract translation: 输出驱动电路通过输出端子将输出电流输出到并入车辆的螺线管。 连接在输出端子和输出驱动电路之间的检测电阻。 放大单元，被配置为输出通过放大检测电阻器的两端之间的电压而产生的模拟检测信号。 配置为输出参考电流的电流产生电路。 连接在电流产生电路和地之间并被配置为根据参考电流输出参考电压的参考电阻。 A / D转换器，被配置为使用参考电压作为参考将模拟检测信号转换成数字检测信号。 一种控制电路，被配置为根据数字检测信号来控制从输出驱动电路输出的输出电流。

公开(公告)号：US20130198539A1

公开(公告)日：2013-08-01

申请号：US13754982

申请日：2013-01-31

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki FURUYA ,  Osamu WATANABE ,  Satoshi KONDO

IPC: G06F1/32

CPC classification number: G06F11/0757 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3234 ,  G06F11/0721 ,  G06F11/079 ,  Y02D50/20

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract translation: 公开了一种用于微机监控系统的看门狗定时器电路。 该电路包括响应于接收到用于对其进行计数的计数时钟信号的定时器电路，以及定时器控制电路，其与定时器刷新指令（prun）同步地加载外部输入的数据信号（stn），并且在其中保持顺序加载 最新的多位数据信号作为参考数据。 当参考数据与预定义模式一致时，同时满足另一个预定条件时，定时器控制电路中断定时器电路的时钟信号计数操作。 在计数操作中断期间，当参考数据与预定义模式不一致时，或者当上述另一个预定条件不满足时，控制电路允许定时器电路重启时钟信号计数操作。

公开(公告)号：US20180032391A1

公开(公告)日：2018-02-01

申请号：US15711000

申请日：2017-09-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki FURUYA ,  Osamu WATANABE ,  Satoshi KONDO

IPC: G06F11/07 ,  G06F1/24 ,  G06F1/32

CPC classification number: G06F11/0757 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3234 ,  G06F11/0721 ,  G06F11/079 ,  Y02D50/20

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.