公开(公告)号：US10379931B2

公开(公告)日：2019-08-13

申请号：US15450197

申请日：2017-03-06

申请人： Renesas Electronics Corporation

发明人： Hirotaka Motai ,  Yasuhiro Tawara ,  Koji Adachi ,  Hitoshi Suzuki

IPC分类号： G06F9/455 ,  G06F11/07 ,  G06F11/14 ,  G06F9/4401 ,  G06F11/30 ,  G06F9/30 ,  G06F9/38 ,  G06F13/24 ,  G06F13/40

摘要： A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

公开(公告)号：US20170046155A1

公开(公告)日：2017-02-16

申请号：US15340481

申请日：2016-11-01

申请人： Renesas Electronics Corporation

发明人： Koji Adachi ,  Kazunori Miyamoto

IPC分类号： G06F9/30 ,  G06F9/48

CPC分类号： G06F9/3005 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/4893 ,  Y02D10/24

摘要： A multi-thread processor including a plurality of hardware threads each of which is configured to generate an independent instruction flow, a thread scheduler configured to output a thread selection signal according to a schedule, the thread selection signal being a signal for selecting a hardware thread to be used in a next execution cycle from among the plurality of hardware threads, a first selector configured to select and output an instruction generated by the hardware thread selected according to the thread selection signal, and an arithmetic circuit configured to execute the instruction output from the first selector. The thread scheduler selects at least one hardware thread selected in a fixed manner from among the plurality of hardware threads in a predetermined first execution period and selects an arbitrary hardware thread in a second execution period other than the first execution period.

摘要翻译： 一种多线程处理器，包括多个硬件线程，每个硬件线程被配置为生成独立的指令流程，线程调度器被配置为根据时间表输出线程选择信号，所述线程选择信号是用于选择硬件线程的信号 在多个硬件线程的下一个执行周期中使用的第一选择器，被配置为选择并输出由根据线程选择信号选择的硬件线程生成的指令的第一选择器，以及被配置为执行从 第一选择器。 线程调度器在预定的第一执行周期内从多个硬件线程中选择固定方式选择的至少一个硬件线程，并且在第一执行周期以外的第二执行周期中选择任意的硬件线程。

公开(公告)号：US20130297916A1

公开(公告)日：2013-11-07

申请号：US13859200

申请日：2013-04-09

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hitoshi Suzuki ,  Koji Adachi

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/3009 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/5077 ,  G06F2209/5018

摘要： A related art semiconductor device suffers from a problem that a processing capacity is decayed by switching an occupied state for each partition. A semiconductor device according to the present invention includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread without depending on the thread schedule as the partition indicated by a first occupation control signal according to a first occupation control signal output when the execution unit executes a first occupation start instruction.

摘要翻译： 相关技术的半导体器件存在通过切换每个分区的占用状态而使处理能力衰减的问题。 根据本发明的半导体器件包括执行算术指令的执行单元和包括多个第一设置寄存器的调度器，每个第一设置寄存器定义硬件线程和分区之间的对应关系，并且基于分区调度生成线程选择信号 和线程计划。 调度器根据当执行单元执行第一占用开始指令时输出的第一占用控制信号，输出指定特定硬件线程的线程选择信号，而不依赖于作为由第一占用控制信号指示的分区的线程调度。

公开(公告)号：US10884882B2

公开(公告)日：2021-01-05

申请号：US16121327

申请日：2018-09-04

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hidekazu Bingo ,  Koji Adachi ,  Yoichi Yuyama

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F9/455 ,  G06F9/52

摘要： A semiconductor device includes a common resource commonly used by plural processes executed on a processor, a semaphore controlling the possessory right of the common resource, and a semaphore management unit performing a process of acquiring the possessory right of the common resource to the semaphore in response to a request of a process performed on the processor. When a request to acquire the possessory right of the common resource is received from a first process in the plural processes and the possessory right cannot be obtained, the semaphore management unit switches the process executed on the processor to a second process, repeatedly performs a process of acquiring the possessory right requested by the first process to the semaphore and, when the possessory right requested by the first process is obtained, switches the process on the processor from the second process to the first process.

公开(公告)号：US10467053B2

公开(公告)日：2019-11-05

申请号：US15805255

申请日：2017-11-07

申请人： Renesas Electronics Corporation

发明人： Junichi Sato ,  Koji Adachi ,  Yousuke Nakamura

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06F9/46

摘要： A multi-thread processor includes a plurality of hardware threads that generates a plurality of mutually independent instruction streams, respectively and a scheduler that schedules the plurality of hardware threads.

公开(公告)号：US09841996B2

公开(公告)日：2017-12-12

申请号：US15393368

申请日：2016-12-29

申请人： Renesas Electronics Corporation

发明人： Junichi Sato ,  Koji Adachi ,  Yousuke Nakamura

IPC分类号： G06F9/48 ,  G06F9/38

CPC分类号： G06F9/4881 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/4887 ,  Y02D10/24

摘要： The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. A thread waste counter is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling. When the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.

公开(公告)号：US20170177431A1

公开(公告)日：2017-06-22

申请号：US15450197

申请日：2017-03-06

申请人： Renesas Electronics Corporation

发明人： Hirotaka Motai ,  Yasuhiro Tawara ,  Koji Adachi ,  Hitoshi Suzuki

IPC分类号： G06F11/07 ,  G06F9/30 ,  G06F9/38 ,  G06F13/40 ,  G06F13/24

CPC分类号： G06F11/0772 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/4405 ,  G06F9/455 ,  G06F9/45533 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3027 ,  G06F13/24 ,  G06F13/4027 ,  G06F13/4068 ,  G06F2201/84

摘要： A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

公开(公告)号：US09501320B2

公开(公告)日：2016-11-22

申请号：US14092498

申请日：2013-11-27

申请人： Renesas Electronics Corporation

发明人： Koji Adachi ,  Kazunori Miyamoto

IPC分类号： G06F9/48 ,  G06F9/38

CPC分类号： G06F9/3005 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/4893 ,  Y02D10/24

摘要： A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread. The thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably selected hardware thread in a second execution period other than the first execution period. A time ratio between the predetermined first execution period and the second execution period is set according to processing requests.

摘要翻译： 一种多线程处理器，包括生成独立指令流的多个硬件线程，根据调度输出线程选择信号的线程调度器，指定要在下一执行中执行的硬件线程的线程选择信号 在多个硬件线程之间循环，以及第一选择器，其根据线程选择信号选择多个硬件线程中的一个，并输出由所选择的硬件线程生成的指令。 线程调度器指定在预定的第一执行周期中在多个硬件线程中预先选择的至少一个硬件线程的执行，并且在除了第一执行周期之外的第二执行周期中指定可变选择的硬件线程的执行。 根据处理请求设定预定的第一执行期间和第二执行期间之间的时间比。

公开(公告)号：US20140109098A1

公开(公告)日：2014-04-17

申请号：US14054418

申请日：2013-10-15

申请人： Renesas Electronics Corporation

发明人： Junichi SATO ,  Koji Adachi ,  Yousuke Nakamura

IPC分类号： G06F9/48

CPC分类号： G06F9/4881 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/4887 ,  Y02D10/24

摘要： The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.

摘要翻译： 调度器执行对多个硬件线程中指定包含在第一组中的每个硬件线程的重复处理的线程调度，用于硬件线程预先设置的次数，以及指定第二组中的任何一个硬件线程 针对包含其他硬件线程的第二组提前设置的次数。 此外，当由线程调度指定的第一组中的硬件线程不可分散时，调度器执行重新安排第二组中的硬件线程的重新调度，而不是第一组中的硬件线程。

公开(公告)号：US10545892B2

公开(公告)日：2020-01-28

申请号：US13830663

申请日：2013-03-14

申请人： Renesas Electronics Corporation

发明人： Koji Adachi ,  Kazunori Miyamoto

IPC分类号： G06F13/26

摘要： A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated.