公开(公告)号：US20180076313A1

公开(公告)日：2018-03-15

申请号：US15640375

申请日：2017-06-30

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Shigeaki SAITO ,  Daisuke TANIGUCHI ,  Natsuo YAMAGUCHI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7802 ,  H01L21/2205 ,  H01L21/2251 ,  H01L21/2253 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/8611

Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

公开(公告)号：US20160079079A1

公开(公告)日：2016-03-17

申请号：US14950200

申请日：2015-11-24

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Daisuke TANIGUCHI

IPC: H01L21/306 ,  H01L21/02 ,  H01L23/544 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract translation: 功率MOSFET的制造方法在两个连续的抛光步骤之间使用在晶片表面的一部分上的硬掩模膜作为抛光停止器。 在晶片的至少划片区域中存在用于形成沟槽的硬掩模膜的状态下进行嵌入式外延生长之后，通过使用硬掩模膜作为阻挡层进行一次抛光，然后在 去除硬掩模膜。

公开(公告)号：US20140206162A1

公开(公告)日：2014-07-24

申请号：US14154260

申请日：2014-01-14

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Daisuke TANIGUCHI

IPC: H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

Abstract translation: 功率MOSFET的制造方法在两个连续的抛光步骤之间使用在晶片表面的一部分上的硬掩模膜作为抛光停止器。 在晶片的至少划片区域中存在用于形成沟槽的硬掩模膜的状态下进行嵌入式外延生长之后，通过使用硬掩模膜作为阻挡层进行一次抛光，然后在 去除硬掩模膜。